1. Field of the Invention
The present invention relates to an asynchronous signal input apparatus which surely receives input signals or data of various sampling rates, and a sampling frequency conversion apparatus which converts input data of a certain sampling frequency into data of a different sampling frequency, and outputs the data thus converted.
2. Description of Related Art
In a known example of sampling frequency converter which receives an asynchronous input signal and converts it into a signal of a certain sampling frequency, data are sequentially written into a memory called FIFO each time a data write command PUSH is supplied, and data that have been stored are read from the FIFO each time a data read command POP is supplied. FIG. 1 shows the construction of such a sampling frequency converter using FIFO.
In order to store data in the FIFO shown in FIG. 1, data is supplied to an input terminal In of the FIFO 1, and a command PUSH is supplied at the same time. Upon receipt of the command PUSH, a W counter 2 produces a write address that designates a location in the FIFO 1, and the write address is supplied to a write address input terminal WAdd of the FIFO 1. In the meantime, the command PUSH serving as a write enable signal WE is supplied to the FIFO 1. As a result, the input data is stored at the location in the FIFO 1 designated by the write address supplied thereto. This input operation under the command PUSH may be carried out at a sampling frequency of 44.1 kHz, for example.
In order to read data from the FIFO, on the other hand, a command POP is supplied. Then, an R counter 3 produces a read address that designates a location in the FIFO 1, and the read address thus produced is supplied to a read address input terminal RAdd of the FIFO 1. In the meantime, the command POP serving as a read enable signal RE is supplied to the FIFO 1. As a result, data stored at the read address is generated from the FIFO 1. This output operation under the command POP may be carried out at a sampling frequency of 48 kHz, for example.
A state monitor unit 4 monitors counter values (addresses) of the W counter 2 and R counter 3, and sends out a control signal to an AND circuit 5 to make the command POP effective or non-effective, so as to hold the read address so that the read address does not exceed the write address. When a command POP is made non-effective, a read enable signal RE is given to the FIFO 1 while the value of the R counter is being maintained or unchanged, so that the same data as that read upon receipt of the last command POP is repeatedly read from the FIFO 1. Thus, the sampling frequency converter of FIG. 1 is constructed so as to repeatedly read the same data while holding the read address, so that the sampling frequency can be increased. If the sampling frequency is to be lowered, however, some sets of the data stored in the FIFO 1 need to be skipped while they are being read.
FIG. 2 shows the construction of a sampling frequency conversion circuit disclosed in Japanese Laid-Open Utility Model Publication (Kokai) No. 654323. The sampling frequency conversion circuit shown in FIG. 2 is adapted to convert input data Din into data Dout having a different sampling frequency from that of the input data Din. In the sampling frequency conversion circuit, data Din is subjected to linear interpolation based on a master clock CKM and a clock CKout received from the outside of the circuit, using time difference information representing a difference between sampling points of data Din and sampling points of data Dout. This example shows a method of converting sampling frequency without using FIFO, for reference.
In the known sampling frequency converter (FIG. 1) using the FIFO as described above, the sampling frequency of the input data is somewhat shifted from that of the output data, and therefore the FIFO 1 may become empty or full during a long-time operation. In view of such situations, the state monitor unit 4 controls the read address so as to continuously output the same data in a hold mode, or skip a part of the data. FIG. 3 shows waveforms of input and output signals (data) received or generated by the known sampling frequency converter. As shown in FIG. 3, in the known sampling frequency converter using the FIFO, the output signal (indicated by a dotted line) is deformed (causing occurrence of noises) as compared with the input signal (indicated by a solid line).
In the meantime, the sampling frequency converter (FIG. 2) using the time difference information merely performs linear interpolation, and thus suffers from low interpolation accuracy.
As a developed form of the apparatus of FIG. 2 for improving the interpolation accuracy, a method of combining oversampling and linear interpolation as shown in FIG. 4 may be considered. In the method using oversampling in addition to linear interpolation, when data of a new sampling point X is calculated through linear interpolation, data of oversampling points A, B adjacent to the new sampling point X are used, instead of data of old sampling points indicated by circles, as shown in FIG. 6, thus achieving high accuracy of interpolation.
FIG. 5 schematically illustrates the method of combining oversampling and linear interpolation. The upper part of FIG. 5 shows an arrangement in which an octuple oversampling operation is performed based on four sets of sampling data, and the lower part shows an arrangement in which linear interpolation is performed based on two oversampling values calculated in the upper part. In the upper part of FIG. 5, symbols D1, D2, D3, D4 each denote a single-sample delay unit, which transfers input data to the later stage in response to a sampling clock (44.1 kHz in this example). With regard to coefficients Cij (i=1-4, j=0-7), subscript "i" represents a coefficient to be given to data from the delay unit Di, namely, a coefficient by which the data Di is multiplied, and subscript "j" represents a coefficient for calculating a value of a j-th oversampling point. Namely, data of the j-th oversampling point is calculated using four coefficients having the same j value. Also, data of eight oversampling points are calculated using a total of eight sets of coefficients where each set consists of four coefficients having the same j value. Based on the data of two oversampling points thus calculated, a linear interpolation block in the lower part calculates data representative of a certain position between the two oversampling points, through linear interpolation. Thus, the calculation of two oversampling values and the linear interpolation are performed at a frequency corresponding to a new sampling frequency (48 kHz in this example), to thus enable highly accurate sampling frequency conversion.
In the sampling frequency converter of FIG. 5 as described above, highly accurate calculations are needed for oversampling, and further, two-step operations are required for calculating oversampling values A, B so as to obtain an interpolated value X between the two points. Furthermore, a hardware to perform operations for linear interpolation is also required. Thus, the known sampling frequency converter requires an increased time of operations, and a large-sized hardware, resulting in an increase in the cost.